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# Created by write_sdc
# Mon Jul  1 03:19:36 2024
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current_design sha256
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# Timing Constraints
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create_clock -name clk -period 2.0000 [get_ports {clk}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[0]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[1]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[2]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[3]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[4]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[5]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[6]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {address[7]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {cs}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {reset_n}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {we}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[0]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[10]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[11]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[12]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[13]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[14]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[15]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[16]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[17]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[18]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[19]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[1]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[20]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[21]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[22]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[23]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[24]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[25]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[26]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[27]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[28]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[29]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[2]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[30]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[31]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[3]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[4]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[5]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[6]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[7]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[8]}]
set_input_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {write_data[9]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {error}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[0]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[10]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[11]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[12]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[13]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[14]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[15]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[16]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[17]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[18]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[19]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[1]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[20]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[21]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[22]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[23]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[24]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[25]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[26]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[27]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[28]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[29]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[2]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[30]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[31]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[3]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[4]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[5]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[6]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[7]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[8]}]
set_output_delay 0.4000 -clock [get_clocks {clk}] -add_delay [get_ports {read_data[9]}]
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# Environment
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# Design Rules
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